System Designs for semiconductor devices such as ASICs or FPGAs, incorporate several different intellectual property (IP) blocks into a single design. IP blocks are individual functional IC components that may be reused from one system design to another. Each IP block may have its own functionality and characteristics independent of other IP blocks in the system design. A bus may be used to provide an interface for connecting several different IP blocks in a given system design. In order to ensure that the IP blocks are properly communicating amongst each other, the bus provides a set of protocols which each IP block must adhere to when communicating with the bus. The system design thus includes IP cores and communication architecture (e.g., bus).
Simulation of a system design may be used to test different characteristics of the system design prior to deployment. This may be done by providing a model for each IP block and simulating the entire system design using the individual IP block models. In order to ensure that the simulation of the system design is accurate, the model for each IP block must be pin-accurate and bus-cycle accurate. Pin-accurate refers to the model being able to characterize data flow down to the granularity of individual pins. Bus cycle accurate refers to the model being able to represent cycle accuracy correctly for transaction communication on the bus interface in accordance with the protocols provided by the bus. A pin-accurate and bus-cycle accurate model can replace a cycle accurate model without affecting functional correctness of IP core and communication architecture simulation while maintaining acceptable variations in timing characteristics.